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from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *

from m5.objects.BaseCPU import BaseCPU
from m5.objects.FUPool import *
#from m5.objects.O3Checker import O3Checker
from m5.objects.BranchPredictor import *
from m5.SimObject import *

class SMTFetchPolicy(ScopedEnum):
    vals = [ 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]

class SMTQueuePolicy(ScopedEnum):
    vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]

class CommitPolicy(ScopedEnum):
    vals = [ 'RoundRobin', 'OldestReady' ]

class ROBWalkPolicy(ScopedEnum):
    vals = [ 'Rollback', 'Replay', 'ConstCycle', 'NaiveCpt', 'ConfidentCpt' ]

class BaseO3CPU(BaseCPU):
    type = 'BaseO3CPU'
    cxx_class = 'gem5::o3::CPU'
    cxx_header = 'cpu/o3/dyn_inst.hh'
    cxx_exports = [
        PyBindMethod("addHintDownStream"),
    ]

    def __init__(self, **kwargs):
        super().__init__(**kwargs)
        self._downstream_pf = []

    # Override the normal SimObject::regProbeListeners method and
    # register deferred event handlers.
    def regProbeListeners(self):
        print("Registering probe listeners for BaseO3CPU {}".format(self))
        assert len(self._downstream_pf) <= 1
        if len(self._downstream_pf):
            self.getCCObject().addHintDownStream(self._downstream_pf[0].getCCObject())
        self.getCCObject().regProbeListeners()

    def add_pf_downstream(self, other_prefetcher):
        if not isinstance(other_prefetcher, SimObject):
            raise TypeError("other_prefetcher must be a SimObject type")
        self._downstream_pf.append(other_prefetcher)

    @classmethod
    def memory_mode(cls):
        return 'timing'

    @classmethod
    def require_caches(cls):
        return True

    @classmethod
    def support_take_over(cls):
        return True

    activity = Param.Unsigned(0, "Initial count")

    cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
          "Constrains stores only.")
    cacheLoadPorts = Param.Unsigned(200, "Cache Ports. "
          "Constrains loads only.")

    decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
    renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
    iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
                                   "delay")
    commitToFetchDelay = Param.Cycles(3, "Commit to fetch delay")
    fetchWidth = Param.Unsigned(16, "Fetch width")
    fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
    fetchQueueSize = Param.Unsigned(48, "Fetch queue size in micro-ops "
                                    "per-thread")

    renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
    iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
                                    "delay")
    commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
    fetchToDecodeDelay = Param.Cycles(4, "Fetch to decode delay")
    decodeWidth = Param.Unsigned(6, "Decode width")

    iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
                                    "delay")
    commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
    decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
    renameWidth = Param.Unsigned(6, "Rename width")

    commitToIEWDelay = Param.Cycles(1, "Commit to "
               "Issue/Execute/Writeback delay")
    renameToIEWDelay = Param.Cycles(1, "Rename to "
               "Issue/Execute/Writeback delay")
    executeToWriteBackDelay = Param.Cycles(1, "Execute to issue delay")

    dispWidth = Param.Unsigned(6, "Each DispQue dispatch width")
    wbWidth = Param.Unsigned(20, "Writeback width")

    iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
               "delay")
    renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
    commitWidth = Param.Unsigned(8, "Commit width")

    squashWidth = Param.Unsigned(8, "Squash width with rollback rob walk")
    replayWidth = Param.Unsigned(8, "Squash width with redo rob walk")
    ConstSquashCycle = Param.Unsigned(1, "Squash width with redo rob walk")
    robWalkPolicy = Param.ROBWalkPolicy('Replay', "Squash with a specific policy")

    trapLatency = Param.Cycles(13, "Trap latency")
    fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")

    backComSize = Param.Unsigned(10,
            "Time buffer size for backwards communication")
    forwardComSize = Param.Unsigned(10,
            "Time buffer size for forward communication")

    LQEntries = Param.Unsigned(80, "Number of load queue entries")
    SQEntries = Param.Unsigned(64, "Number of store queue entries")

    SbufferEntries = Param.Unsigned(16, "Number of store buffer entries")
    SbufferEvictThreshold = Param.Unsigned(8, "store buffer eviction threshold")
    storeBufferInactiveThreshold = Param.Unsigned(800, "store buffer writeback timeout threshold")

    LSQDepCheckShift = Param.Unsigned(0,
            "Number of places to shift addr before check")
    LSQCheckLoads = Param.Bool(True,
        "Should dependency violations be checked for "
        "loads & stores or just stores")
    store_set_clear_period = Param.Unsigned(250000,
            "Number of load/store insts before the dep predictor "
            "should be invalidated")
    LFSTSize = Param.Unsigned(2048, "Last fetched store table size")
    store_set_clear_thres = Param.Unsigned(1048576,"")
    LFSTEntrySize = Param.Unsigned(4,"The number of store table inst in every entry of LFST can contain")
    SSITSize = Param.Unsigned(8192, "Store set ID table size")
    BankConflictCheck = Param.Bool(True, "open Bank conflict check")


    numRobs = Param.Unsigned(1, "Number of Reorder Buffers");

    numPhysIntRegs = Param.Unsigned(224,
            "Number of physical integer registers")
    numPhysFloatRegs = Param.Unsigned(192, "Number of physical floating point "
                                      "registers")
    numPhysVecRegs = Param.Unsigned(192, "Number of physical vector "
                                      "registers")
    numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate "
                                      "registers")

    # most ISAs don't use condition-code regs, so default is 0
    numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers")
    numPhysRMiscRegs = Param.Unsigned(40, "Number of physical renameable misc registers")

    numDQEntries = Param.Unsigned(18, "Number of entries in the dispQue")
    numROBEntries = Param.Unsigned(320, "Number of reorder buffer entries")

    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
    smtFetchPolicy = Param.SMTFetchPolicy('RoundRobin', "SMT Fetch policy")
    smtLSQPolicy    = Param.SMTQueuePolicy('Partitioned',
                                           "SMT LSQ Sharing Policy")
    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
    smtIQPolicy    = Param.SMTQueuePolicy('Partitioned',
                                          "SMT IQ Sharing Policy")
    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
    smtROBPolicy   = Param.SMTQueuePolicy('Partitioned',
                                          "SMT ROB Sharing Policy")
    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
    smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy")

    branchPred = Param.BranchPredictor(DecoupledBPUWithFTB(),
                                       "Branch Predictor")
    needsTSO = Param.Bool(False, "Enable TSO Memory model")

    scheduler = Param.Scheduler(KunminghuScheduler(), "")

    arch_db = Param.ArchDBer(Parent.any, "Arch DB")

    store_prefetch_train = Param.Bool(True, "Training store prefetcher with store addresses")

